View QL5130-33APQ208C_7353782.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2005 quicklogic corporation www.quicklogic.com ? 1 ? device highlights high performance pci controller 32-bit/33 mhz pci target zero-wait-state pci target provides 132 mbps transfer rates programmable backend interface to optional local processor independent pci bus (33 mhz) and local bus (up to 160 mhz) clocks fully customizable pci configuration space configurable fifos with depths up to 128 reference design with driver code (win 95/98/2000/nt4.0) available pci v2.2 compliant supports type 0 configuration cycles 3.3 v and 5 v tolerant pci signaling supports universal pci adapter designs 3.3 v cmos in 144-pin tqfp, 208-pin pqfp and 256-pbga supports endian conversions unlimited continuous burst transfers supported extendable pci functionality support for configuration space from 0x40 to 0x3ff power management, compact pci, hot- swap/hot-plug compatible pci v2.2 power management spec compatible pci v2.2 vital product data (vpd) configuration support programmable logic 57 k system gates/619 logic cells 13,824 ram bits, up to 157 i/o pins 250 mhz 16-bit counters , 275 mhz datapaths, 160 mhz fifos all backend interface and glue-logic can be implemented on chip six 64-deep fifos (two rams each) or three 128-deep fifos (four rams each) or a combination that requires twelve or less quicklogic ram modules two 32-bit busses interface between the pci controller and the programmable logic figure 1: ql5130 block diagram pci bus pci bus 33/66 mhz/32 bits (data and address) target controller 160 mhz fifos config. space high speed logic cells (57 k gates) high speed data path programmable logic 32 bit interface 157 user i/o 33 mhz/32-bit pci ta rget with embedded programmable logic and dual port sram ql5130 quickpci data sheet
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 2 architecture overview the ql5130 device in the quicklogic quickpci embedded standard pr oduct (esp) family provides a complete and customizable pci interf ace solution combined with 57,000 sy stem gates of programmable logic. this device eliminates any need for the designer to worry about pci bus compliance, yet allows for the maximum 32-bit pci bus bandwidth (132 mbps). the programmable logic portion of the device contai ns 619 quicklogic logic cells and 12 quicklogic dual port ram blocks. these configurable ram blocks can be configured in many width/depth combinations. they can also be combined with logic cells to form fifos, or be initialized via serial eeprom on power-up and used as roms. see ram module features on page 8 for more information. the ql5130 device meets pci v2.2 electrical and timing specifications and has b een fully hardware-tested. the ql5130 device features 3.3 v operation with multi-volt compatible i/os. therefore, it can easily operate in 3.3 v systems and is fully compatible with 3.3 v, 5 v and universal pci card development. pci interface the pci target is pci v2.2 compliant and supports 32-bi t/33 mhz operation. it is capable of zero wait-state infinite-length read and write transactions (132 mbps). transaction control is available via the user interface as retries, wait-states, or premature transaction termination may be induced if necessary. the pci configuration registers are implemented in the programma ble region of the device, leaving the designer with ample flexibility to su pport optional features. the ql5130 device supports maximum 32-bit pci transfer ra tes, so many applications exist which are ideally suited to the device's high performance. high-s peed data communications, telecommunications, and computing systems are just a few of the broad range of ap plications areas that can benefit from the high speed pci interface and programmable logic. pci configuration space the ql5130 supports customization of required configuration registers such as vendor id, device id, subsystem vendor id, etc. quicklogic provides a reference configuration space design block. since the pci configuration registers are implemen ted in the programmable region of the ql5130, the designer can implement optional features such as mult iple 32-bit base address regi sters (bars) and multiple functions, as well as support the following pci co mmands: i/o read, i/o write, memory read, memory write, config read (required), configuration write (req uired), memory read multip le, memory read line, and memory write and invalidate. additionally, the device supports extended capabili ties registers, expansion roms, power management, compactpci ho t-plug/hot-swap, vital product data, i 2 0, and mailbox registers. address and command decode pci address and command decoding is performed by lo gic in the programmable sect ion of the device. this allows support for any size of memory or i/o space for ba ckend logic. it also allows the designer to implement any subset of the pci commands su pported by the ql5130. quicklogic provides a reference address register/counter and command decode block.
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 3 ram architecture overview the ram modules in the programmable region can be used to create configurable 32-bit fifos. each 32-bit fifo can be independently assigned to target address space for read pre-fetch or write posting. using the 12 quicklogic ram modules, the combinations include: six independent 64-deep fifo (two rams each), or three independent 128-deep fifos (four rams each), or a combination of the above that requires 12 or less quicklogic ram modules asynchronous fifos (with independent read and write clocks) are also supported. quickworks ? spde tm has a creation wizard that is used to create fifos as shown in figure 2 . figure 2: graphical in terface to create fifo
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 4 internal pci interface the symbol used to connect to the pc i interface of the ql5130 is shown in figure 3 . this symbol is used in schematic or mixed schema tic/hdl design flows in the quickworks software. figure 3: pci interface symbol
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 5 internal interface signal descriptions signals used to connect to the pci in terface in the ql5130 are described in table 1 . the direction of the signal indicates if it is an input provided by the local in terface (i) or an output provided by the pci interface (o). table 1: ql5130 pci32t target interface signals signal type description usr_addr_wrdata[31:0] o target address and target write data. duri ng all target accesses, the address is presented on usr_addr_wrdata[ 31:0] at the same time usr_adr_valid is active. during target write transactions, this port also presents valid write data to the pci configuration space or user logic when usr_adr_inc is active. during master read transactions, this port also presents valid data read from pci to the backend. this is the registered version of the pci ad[31:0] signal. usr_cbe[3:0] o pci command and byte enables. during target accesses, the pci command is presented on usr_cbe[3:0] at t he same time usr_adr_valid is active. this port also presents active-low byte enables to the pci configuration space or user logic. this is the registered version of the pci cben[3:0] signal. usr_adr_valid o indicates the beginning of a pci transaction, and that a target address is valid on usr_addr_wrdata[31:0] and the pci command is valid on usr_cbe[3:0]. when this signal is active, the target address must be latched and decoded to determine if this address belongs to the device memory or i/o space. also, the pci command must be decoded to determine the type of pci transaction. on subsequent clocks of a target access, this signal is low, indicating that the address is no longer on usr_addr_wrd ata[31:0]. usr_adr_inc o this signal, when asserted, indicates that the target address should be incremented, because the previous data transfer has completed. during burst target accesses, the target address is only presented to the backend at the beginning of the transaction when usr_adr_valid is active, and must therefore be latched and incremented (by 4) for subsequent data transfers. for target write transactions, usr_adr_inc indicates valid data on usr_addr_wrdata[31:0] that must be accepted by the backend logic (regardless of the state of usr_rdy). for read transactions, us r_adr_inc signals to the backend that the core has presented the read data on the pci bus (has asserted trdyn). usr_rddecode i this signal must be asserted by the backend when a user read command (e.g., memory read, memory read line, memory read multiple, i/o read, etc.) has been decoded from usr_cbe[3:0]. it is ac knowledged by the core only when usr_adr_valid is active. usr_wrdecode i this signal must be asserted by the backend when a user write command (e.g., memory write, memory write and invalidat e, i/o write, etc.) has been decoded from usr_cbe[3:0]. it is acknowledged by the core only when usr_adr_valid is active. usr_select i this signal must be driven active when the address on usr_addr_wrdata[31:0] has been decoded and determined to be within the address space of the device. usr_addr_wrdata[31:0] must be compared to each of the valid base address registers in the pci configuration space. also, this signal must be gated by the memory access enable or i/o access enab le registers in the pci configuration space (command register bits 1 or 0 at offset 04h). this signal is acknowledged by the core only when usr_adr_valid is active. usr_write o this signal is active throughout a ?user write? transaction, which has been decoded by usr_wrdecode at the beginning of the transaction. the write strobe for individual dwords of data (on usr_addr_wrdata[31:0]) during a user write transaction should be generated by logically anding this signal with usr_adr_inc.
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 6 cfg_write o this signal is active throughout a ?configur ation write? transaction. the write strobe for individual dwords of data (on usr_addr_wrdata[31:0]) during a configuration write transaction should be generated by logically anding this signal with usr_adr_inc. cfg_rddata[31:0] i data from the pci configuration regist ers, required to be presented during pci configuration reads. usr_rddata[31:0] i data from the backend, required to be presented during user reads. cfg_cmdreg6 i bits 6 from the command register in the pc i configuration space (offset 04h). parity error response. if high, the core uses perrn to report data parity errors. otherwise the core always tristates perrn. cfg_cmdreg8 i bits 8 from the command register in th e pci configuration space (offset 04h). serrn enable. if high, the core uses serrn to report address parity errors if cfg_cmdreg6 is high. otherwise the core always tristates serrn. cfg_perr_det o parity error detected on the pci bus. when this signal is active, bit 15 of the status register must be set in the pci configuration space (offset 04h). cfg_serr_sig o system error asserted on the pci bus. when this signal is active, the signaled system error bit, bit 14 of the status regi ster, must be set in the pci configuration space (offset 04h). usr_trdyn o copy of the trdyn signal as driven by the pci target interface. valid only within target accesses to the core. usr_stopn o copy of the stopn signal as driven by the pci target interface. valid only within target accesses to the core. usr_devsel o inverted copy of the devseln signal as driven by the pci target interface. valid only within target acce sses to the core. usr_last_cycle_d1 o active one clock cycle after the last data phase occurs on pci. active only for one clock cycle. usr_rdy i used to delay (add wait states to) a target pci transaction when the backend needs additional time to provide data (read) or accept data (write). subject to pci latency restrictions if pci compliance is needed. usr_stop i used to prematurely stop a pci target access. table 1: ql5130 pci32t target interface signals (continued) signal type description
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 7 array of logic cells a wide range of additional features complements the ql5130 device. the fp ga portion of the device is 5 v and 3.3 v pci-compliant and can pe rform high-speed logic functions such as 160 mhz fifos. i/o pins provide individually controlled output enables, dedicated in put/feedback registers, and full jtag capability for boundary scan and test. in addition, the ql5130 device provides the benefits of nonvolatility, high design security, immediate functionality on power-up, and a single chip solution. the ql5130 programmable logic architecture consists of an array of user-c onfigurable logic building blocks, called logic cells, set beneath a gr id of metal wiring channels simila r to those of a gate array (see figure 4 ). through vialink ? elements located at the wire intersections, th e output(s) of any cell may be programmed to connect to the input(s) of any other cell. using the programmable logic in the ql5130, designers can quickly and easily customize their ?backend? de sign for any number of applications. figure 4: logic cell qs a1 a2 a3 a4 a5 a6 os op b1 b2 c1 c2 ms d1 e1 np e2 d2 ns f1 f3 f5 f6 f2 f4 qc qr mp az oz qz nz fz
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 8 ram module features the ql5130 device has twelve 1,152-bit ram modules , for a total of 13,824 ram bits. using two ?mode? pins, designers can config ure each module into 64 (deep) x18 (wid e), 128x9, 256x4, or 512x2 blocks (see figure 5 ). the blocks are also easily cascadable to increase their effective width or depth. see table 2 for ram mode configurations. figure 5: ram module the ram modules are dual-ported, with completely independent read and write ports and separate read and write clocks. the read ports support asynchro nous and synchronous operation, while the write ports support synchronous operation. each port has 18 da ta lines and 9 address lines, allowing word lengths of up to 18 bits and address spaces of up to 512 wo rds. depending on the mode selected, however, some higher order data or address lines may not be used. the write enable (we) line acts as a clock enable for synchronous write operation. the read enable (re) acts as a clock enable for synchronous read operation (a syncrd input low), or as a flow-through enable for asynchronous read operation (asyncrd input high). designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address line s together and dividing the words between modules. this approach allows up to 512-deep configurations as large as 28 bits wide in the ql5130 device. a similar technique can be used to create depths greater than 512 words. in this case, address signals higher than the eighth bit are encoded onto the write enab le (we) input for write operations. the read data outputs are multiplexed together us ing encoded higher read address bits for the multiplexer select signals. table 2: ram configurations mode address buses [a:0] data buses [w:0] 64x18 [5:0] [17:0] 128x9 [6:0] [8:0] 256x4 [7:0] [3:0] 512x2 [8:0] [1:0] mode[1:0] wa[a:0] wd[w:0] we wclk asyncrd ra[a:0] rd[w:0] re rclk
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 9 jtag support jtag pins support ieee standard 1149.1a to provide boundary scan capability for the ql5130 device. six pins are dedicated to jt ag and programming functions on each ql5130 device, and are unavailable for general design input and output signals. tdi, tdo, tck, tms, and trstb are jtag pins. a sixth pin, stm, is used only for programming. development tools software support for the ql5130 device is available through the quickworks development package. quickworks is fully integrated into the windows 98, 2000, nt, me and xp operating systems. it provides design, layout, pre- and post-layout simulation an d external stimulus design tools as shown in figure 6 . the program that links all these applications together and ac ts as the design flow manager is called seamless pasic design environment (spde). the term ?pasic? is a re gistered trademark of quicklogic corporation and refers to a quicklogic fp ga, or ?programmable asic.? quickworks can be used to perform the fo llowing functions in the design process: design pre-layout simulation synthesis placement and optimization post-layout simulation
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 10 figure 6: quickworks design flow the unix-based quicktools ? package is a subset of quickworks an d provides a solution for designers who use schematic-only design flow third-party tools for de sign entry, synthesis, or simulation. quicktools reads edif netlists and provides support fo r all quicklogic devices. quicktools also supports a wide range of third- party modeling and simulation tools.
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 11 electrical specifications dc characteristics the dc specifications are provided in table 3 through table 5 . table 3: absolute maximum ratings parameter value parameter value vcc voltage -0.5 v to 4.6 v dc input current 20 ma vccio voltage -0.5 v to 7.0 v esd pad protection 2000 v input voltage -0.5 v to vccio + 0.5 v storage temperature -65c to + 150c latch-up immunity 200 ma lead temperature 300 c table 4: operating range symbol parameter industrial commercial unit min max min max vcc supply voltage 3.0 3.6 3.0 3.6 v vccio i/o input tolerance voltage 3.0 5.5 3.0 5.25 v ta ambient temperature -40 85 0 70 c k delay factor -a speed grade 0.43 0.90 0.46 0.88 n/a table 5: dc characteristics symbol parameter conditions min max units vih input high voltage 0.5 vcc vccio+ 0.5 v vil input low voltage -0.5 0.3 vcc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9 vcc v vol output low voltage iol = 16 ma 0.45 v iol = 1.5 ma 0.1 vcc v il i or i/o input leakage current vi = vccio or gnd -10 10 a ioz 3-state output leakage current vi = vccio or gnd -10 10 a ci i/o input capacitance a a. capacitance is sample tested only. clock pins are 12 pf maximum. - - 10 pf ios output short circuit current b b. only one output at a time. duration should not exceed 30 seconds. vo = gnd vo = vcc -15 40 -180 210 ma ma icc d.c. supply current c c. for -a commercial grade device only. maximum icc is 3 ma for all industrial grade devices. for ac conditions, contact quicklogic customer engineering. vi.vio = vccio or gnd 0.50 typ. 2 ma iccio d.c. supply current on vccio 0 100 a
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 12 ac characteristics the ac specifications (at vcc = 3.3 v, ta = 25 c (k = 1.00)) are provided in table 6 through table 13 . (to calculate delays, multiply the appropriate k factor in table 4 operating ranges by the following numbers.) table 6: logic cells symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagat ion delay over process variation at vc c=3.3 v and ta=25c. multiply by the appropriate delay factor, k, for speed grade, voltage and te mperature settings as specif ied in the operating range. 1 2 3 4 5 t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output b b. these limits are derived from a re presentative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for spec ific paths should be determin ed from timing analysis of your particular design. 1.4 1.7 1.9 2.2 3.2 t su setup time: time t he synchronous input of the flip-flop must be stable before the active clock edge b 1.7 1.7 1.7 1.7 1.7 t h hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0.0 0.0 0.0 0.0 0.0 t clk clock-to-q delay: the amount of time taken by the flip- flop to output after the active clock edge. 0.7 1.0 1.2 1.5 2.5 t cwhi clock high time: required minimum time the clock stays high 1.2 1.2 1.2 1.2 1.2 t cwlo clock low time: required minimum time that the clock stays low 1.2 1.2 1.2 1.2 1.2 t set set delay: time between when the flip-flop is ?set? (high) and when the output is consequently ?set? (high) 1.0 1.3 1.5 1.8 2.8 t reset reset delay: time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) 0.8 1.1 1.3 1.6 2.6 t sw set width: time that the set signal must remain high/low 1.9 1.9 1.9 1.9 1.9 t rw reset width: time that the reset signal must remain high/low 1.8 1.8 1.8 1.8 1.8
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 13 table 7: ram cell synchronous write timing symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagation delay over proc ess variation at vcc=3.3 v and ta=25c. multiply by the appropriate delay factor, k, for speed grade, voltage and te mperature settings as specif ied in the operating range. 1 2 3 4 5 t swa wa setup time to wclk: time the write address must be stable before the active edge of the write clock 1.0 1.0 1.0 1.0 1.0 t hwa wa hold time to wclk: time the write address must be stable after the active edge of the write clock 0.0 0.0 0.0 0.0 0.0 t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 1.0 1.0 1.0 1.0 1.0 t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0.0 0.0 0.0 0.0 0.0 t swe we setup time to wclk: time the write enable must be stable before the active edge of the write clock 1.0 1.0 1.0 1.0 1.0 t hwe we hold time to wclk: time the write enable must be stable after the active edge of the write clock 0.0 0.0 0.0 0.0 0.0 t wcrd wclk to rd (wa = ra): time between the active write clock edge and the time when the data is available at rd 5.0 5.3 5.6 5.9 7.1 table 8: ram cell synchronous read timing symbol parameter propagation delays (ns) fanout 1 2 3 4 5 t sra ra setup time to rclk: time the read address must be stable before the active edge of the read clock 1.0 1.0 1.0 1.0 1.0 t hra ra hold time to rclk: ti me the read address must be stable after the active edge of the read clock 0.0 0.0 0.0 0.0 0.0 t sre re setup time to rclk: time the read enable must be stable before the active edge of the read clock 1.0 1.0 1.0 1.0 1.0 t hre re hold time to rclk: time the read enable must be stable after the active edge of the read clock 0.0 0.0 0.0 0.0 0.0 t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd a a. these limits are derived from a repres entative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for specific pa ths should be determined from timing analysis of a particular design. 4.0 4.3 4.6 4.9 6.1
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 14 table 9: ram cell synchronous read timing symbol parameter propagation delays (ns) fanout 1 2 3 4 5 r pdrd ra to rd: time between when the read address is input and when the data is output a a. these limits are derived from a repres entative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for specific pa ths should be determined from timing analysis of a particular design. 3.0 3.3 3.6 3.9 5.1 table 10: input-only cells symbol parameter propagation delays (ns) fanout a a. these limits are derived from a representative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analysis of a particular design. 1 2 3 4 8 12 24 t in high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 t ini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 t isu input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 3.1 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0.0 0.0 0.0 0.0 0.0 0.0 0.0 t iclk input register clock-to-q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 t irst input register reset delay: time between when the flip-flop is ?reset?(low) and when the output is consequently ?reset? (low) 0.6 0.7 0.9 1.0 1.5 2.0 3.5 t iesu input register clock enable setup time: time ?enable? must be stable before the active clock edge 2.3 2.3 2.3 2.3 2.3 2.3 2.3 t ieh input register clock enable hold time: time ?enable? must be stable after the active clock edge 0.0 0.0 0.0 0.0 0.0 0.0 0.0
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 15 table 11: clock cells symbol parameter propagation delays (ns) fanout a a. the array distributed networks consis t of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 8 loads per half column. the global clock has up to 11 loads per half column. 1 2 3 4 8 10 11 t ack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 t gckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 t gckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 table 12: i/o cell input delays symbol parameter propagation delays (ns) fanout a a. these limits are derived fr om a representative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analysis of a particular design. 1 2 3 4 8 10 t i/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 t isu input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0.0 0.0 0.0 0.0 0.0 0.0 t ioclk input register clock-to-q 0.7 1.0 1.2 1.5 2.5 3.0 t iorst input register reset delay: time between when the flip-flop is ?reset?(low) and when the output is consequently ?reset? (low) 0.6 0.9 1.1 1.4 2.4 2.9 t iesu input register clock enable setup time: time ?enable? must be stable before the active clock edge 2.3 2.3 2.3 2.3 2.3 2.3 t ieh input register clock enable hold time: time ?enable? must be stable after the active clock edge 0.0 0.0 0.0 0.0 0.0 0.0
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 16 table 13: i/o cell output delays symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 t outlh output delay low to high (90% of h) 2.1 2.5 3.1 3.6 4.7 t outhl output delay high to low (10% of l) 2.2 2.6 3.2 3.7 4.8 t pzh output delay tri-state to high (90% of h) 1.2 1.7 2.2 2.8 3.9 t pzl output delay tri-state to low (10% of l) 1.6 2.0 2.6 3.1 4.2 t phz output delay high to tri-state a a. the following loads are used for t pxz : 2.0 t plz output delay low to tri-state a 1.2 5 pf 1k ? 5 pf 1k ? tphz tplz
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 17 ql5130 external device pins table 14 describes the different types of devices pins. table 15 describes the external pins on the ql5130 device, some of which connect to the pci bus, and others that are programmable as user io. table 14: pin types type description in input. a standard input-only signal out totem pole output. a standard active output driver t/s tri-state. a bi-directional, tri-state input/output pin s/t/s sustained tri-state. an active low tri-state signal dr iven by one pci agent at a time. it must be driven high for at least one clock before being disabled (set to hi-z). a pull-up needs to be provided by the pci system central resource to sustain the inactive state once the active driver has released the signal. o/d open drain. allows multiple devices to share this pin as a wired-or. table 15: ql5130 external device pins pin/bus name type function vcc in supply pin. tie to 3.3v supply. vccio in supply pin for i/o. set to 3.3v for 3.3v i/o, 5v for 5.0v compliant i/o gnd in ground pin. tie to gnd on the pcb. i/o t/s programmable input/output/tri-state/bi-directional pin. glck/i in programmable global network or input-onl y pin. tie to vcc or gnd if unused. aclk/i in programmable array network or input-onl y pin. tie to vcc or gnd if unused. tdi/rsi a in jtag data in/ram init. serial data in. tie to vcc if unused. connect to serial eprom data for ram init. tdo/rco a out jtag data out/ram init clock. leave unconnected if unused. connect to serial eprom clock for ram init. tck in jtag clock. tie to gnd if unused. tms in jtag test mode select. tie to vcc if unused. trstb/rro a in jtag reset/ram init. reset out. tie to gnd if unused. connect to serial eprom reset for ram init. stm in quicklogic reserved pin. tie to gnd on the pcb. ad[31:0] t/s pci address and data: 32 bit multiplexed address/data bus. cben[3:0] t/s pci bus command and byte enables: multiplexed bus which contains byte enables for ad[31:0] or the bus command during the address phase of a pci transaction. pa r t/s pci parity: even parity across ad[31:0] an d c/ben[3:0] busses. driven one clock after address or data phases. master drives par on address cycles and pci writes. the target drives par on pci reads. framen s/t/s pci cycle frame: driven active by current pci master during a pci transaction. driven low to indicate the address cycle, driven high at the end of the transaction. devseln s/t/s pci device select. driven by a target that has decoded a valid base address. clk in pci system clock input.
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 18 rstn in pci system reset input perrn s/t/s pci data parity error. driven active by the initia tor or target two clock cycles after a data parity error is detected on the ad and c/ben busses. serrn o/d pci system error: driven active when an address cycle parity error, data parity error during a special cycle, or other cata strophic error is detected. idsel in pci initialization device select. use to select a specific pci agent during system initialization. irdyn s/t/s pci initiator ready. indicates the initiator?s ability to complete a read or write transaction. data transfer occurs only on clock cycles where both irdyn and trdyn are active. trdyn s/t/s pci target ready. indicates the target?s ability to complete a read or write transaction. data transfer occurs only on clock cycles where both irdyn and trdyn are active. stopn s/t/s pci stop. used by a pci target to end a burst transaction. a. see quick note 65 at http://quicklogic.com/images/quicknote65.pdf for information on ram initialization. table 15: ql5130 external device pins
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 19 ql5130 - 144 tqfp pinout diagram figure 7: 144-pin tqfp ql5130-33apf144c quickpci pin #73 pin #1 pin #37 pin #109
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 20 ql5130 - 144 tqfp pinout table summary: 47 pci pins, 71 user i/o, 4 gclk, and 2 aclk. table 16: ql5130 - 144 tqfp pinout table pin function pin function pin function pin function 1 i/o 37 ad[21] 73 ad[4] 109 tck 2 i/o 38 tdi/rsi 74 ad[3] 110 stm 3 i/o 39 ad[20] 75 ad[2] 111 i/o 4 i/o 40 ad[19] 76 ad[1] 112 i/o 5 i/o 41 ad[18] 77 ad[0] 113 i/o 6 i/o 42 vcc 78 i/o 114 vcc 7 vcc 43 ad[17] 79 vcc 115 i/o 8 i/o 44 ad[16] 80 i/o 116 i/o 9 i/o 45 cben[2] 81 i/o 117 i/o 10 i/o 46 framen 82 i/o 118 i/o 11 i/o 47 irdyn 83 i/o 119 i/o 12 i/o 48 trdyn 84 i/o 120 i/o 13 i/o 49 devseln 85 i/o 121 i/o 14 i/o 50 gnd 86 i/o 122 gnd 15 gnd 51 stopn 87 gnd 123 i/o 16 i/o 52 perrn 88 i/o 124 i/o 17 gclk/i 53 serrn 89 gclk/i 125 i/o 18 aclk/i 54 gnd 90 aclk/i 126 gnd 19 vcc 55 pa r 91 vcc 127 i/o 20 rstn 56 cben[1] 92 gclk/i 128 i/o 21 clk 57 ad[15] 93 gclk/i 129 i/o 22 vcc 58 vccio 94 vcc 130 vccio 23 i/o 59 ad[14] 95 i/o 131 i/o 24 ad[31] 60 ad[13] 96 i/o 132 i/o 25 ad[30] 61 ad[12] 97 i/o 133 i/o 26 ad[29] 62 ad[11] 98 i/o 134 i/o 27 ad[28] 63 ad[10] 99 i/o 135 i/o 28 ad[27] 64 ad[9] 100 i/o 136 i/o 29 ad[26] 65 ad[8] 101 i/o 137 i/o 30 gnd 66 gnd 102 gnd 138 gnd 31 ad[25] 67 cben[0] 103 i/o 139 i/o 32 ad[24] 68 ad[7] 104 i/o 140 i/o 33 cben[3] 69 ad[6] 105 i/o 141 i/o 34 idsel 70 ad[5] 106 i/o 142 i/o 35 ad[23] 71 trstb/rro 107 i/o 143 tdo/rco 36 ad[22] 72 tms 108 i/o 144 i/o
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 21 ql5130 - 208 pqfp pinout diagram figure 8: 208-pin pqfp QL5130-33APQ208C quickpci pin #1 pin # 53 pin # 105 pin #157
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 22 ql5130 - 208 pqfp pinout table summary: 47 pci pins, 121 user i/o, 4 gclk, and 2 aclk. table 17: ql5130 - 208 pqfp pinout table pin function pin function pin function pin function pin function pin function 1 i/o 36 ad[28] 71 ad[13] 106 i/o 141 i/o 176 i/o 2 i/o 37 ad[27] 72 ad[12] 107 i/o 142 i/o 177 gnd 3 i/o 38 ad[26] 73 gnd 108 i/o 143 i/o 178 i/o 4 i/o 39 ad[25] 74 ad[11] 109 i/o 144 i/o 179 i/o 5 i/o 40 ad[24] 75 ad[10] 110 i/o 145 vcc 180 i/o 6 i/o 41 vcc 76 ad[9] 111 i/o 146 i/o 181 i/o 7 i/o 42 cben[3] 77 ad[8] 112 i/o 147 gnd 182 gnd 8 i/o 43 gnd 78 gnd 113 i/o 148 i/o 183 i/o 9 i/o 44 idsel 79 cben[0] 114 vcc 149 i/o 184 i/o 10 vcc 45 ad[23] 80 ad[7] 115 i/o 150 i/o 185 i/o 11 i/o 46 ad[22] 81 ad[6] 116 gnd 151 i/o 186 i/o 12 gnd 47 ad[2]1 82 ad[5] 117 i/o 152 i/o 187 vccio 13 i/o 48 ad[20] 83 vccio 118 i/o 153 i/o 188 i/o 14 i/o 49 ad[19] 84 ad[4] 119 i/o 154 i/o 189 i/o 15 i/o 50 ad[18] 85 ad[3] 120 i/o 155 i/o 190 i/o 16 i/o 51 ad[17] 86 ad[2] 121 i/o 156 i/o 191 i/o 17 i/o 52 ad[16] 87 ad[1] 122 i/o 157 tck 192 i/o 18 i/o 53 cben[2] 88 ad[0] 123 i/o 158 stm 193 i/o 19 i/o 54 tdi 89 i/o 124 i/o 159 i/o 194 i/o 20 i/o 55 framen 90 i/o 125 i/o 160 i/o 195 i/o 21 i/o 56 irdyn 91 i/o 126 i/o 161 i/o 196 i/o 22 i/o 57 trdyn 92 i/o 127 gnd 162 i/o 197 i/o 23 gnd 58 devseln 93 i/o 128 i/o 163 gnd 198 i/o 24 i/o 59 gnd 94 i/o 129 gclk/i 164 i/o 199 gnd 25 rstn 60 stopn 95 gnd 130 aclk/i 165 vcc 200 i/o 26 aclk/i 61 vcc 96 i/o 131 vcc 166 i/o 201 vcc 27 vcc 62 i/o 97 vcc 132 gclk/i 167 i/o 202 i/o 28 gclk/i 63 i/o 98 i/o 133 gclk/i 168 i/o 203 i/o 29 clk 64 perrn 99 i/o 134 vcc 169 i/o 204 i/o 30 vcc 65 i/o 100 i/o 135 i/o 170 i/o 205 i/o 31 i/o 66 serrn 101 i/o 136 i/o 171 i/o 206 i/o 32 i/o 67 pa r 102 i/o 137 i/o 172 i/o 207 tdo 33 ad[31] 68 cben[1] 103 trstb 138 i/o 173 i/o 208 i/o 34 ad[30] 69 ad[15] 104 tms 139 i/o 174 i/o 35 ad[29] 70 ad[14] 105 i/o 140 i/o 175 i/o
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 23 ql5130 - 256 pbga pinout diagram figure 9: 256-pin pbga 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w bottom view pin a1 corner
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 24 ql5130 - 256 pbga pinout table summary: 47 pci pins, 151 user i/o, 4 gclk, and 2 aclk. table 18: ql5130 - 256 pbga pinout table pin function pin function pin function pin function pin function pin function a1 gnd c4 i/o e19 i/o l2 aclk/i t17 i/o v20 i/o a2 i/o c5 i/o e20 i/o l3 rstn t18 i/o w1 i/o a3 i/o c6 i/o f1 i/o l4 gclk/i t19 nc w2 i/o a4 i/o c7 i/o f2 i/o l17 vcc t20 i/o w3 tdi a5 i/o c8 i/o f3 i/o l18 i/o u1 i/o w4 i/o a6 i/o c9 vccio f4 vcc l19 i/o u2 i/o w5 ad[27] a7 i/o c10 i/o f17 vcc l20 i/o u3 i/o w6 cben[3] a8 i/o c11 i/o f18 nc m1 i/o u4 gnd w7 ad[21] a9 i/o c12 i/o f19 i/o m2 i/o u5 ad[26] w8 ad[20] a10 i/o c13 i/o f20 i/o m3 i/o u6 vcc w9 cben[2] a11 i/o c14 i/o g1 i/o m4 nc u7 ad[22] w10 devseln a12 i/o c15 i/o g2 nc m17 nc u8 gnd w11 perrn a13 i/o c16 i/o g3 i/o m18 i/o u9 framen w12 cben[1] a14 i/o c17 i/o g4 i/o m19 i/o u10 vcc w13 pa r a15 i/o c18 i/o g17 i/o m20 i/o u11 i/o w14 ad[10] a16 i/o c19 i/o g18 i/o n1 i/o u12 i/o w15 ad[9] a17 i/o c20 i/o g19 nc n2 i/o u13 gnd w16 ad[5] a18 i/o d1 i/o g20 i/o n3 i/o u14 ad[11] w17 ad[1] a19 tck d2 i/o h1 i/o n4 gnd u15 vcc w18 ad[0] a20 i/o d3 i/o h2 i/o n17 gnd u16 ad[4] w19 i/o b1 tdo d4 gnd h3 i/o n18 i/o u17 gnd w20 trstb b2 i/o d5 i/o h4 gnd n19 i/o u18 i/o y1 i/o b3 i/o d6 vcc h17 gnd n20 i/o u19 i/o y2 nc b4 i/o d7 i/o h18 i/o p1 i/o u20 i/o y3 i/o b5 i/o d8 gnd h19 i/o p2 i/o v1 i/o y4 ad[31] b6 i/o d9 i/o h20 i/o p3 i/o v2 nc y5 ad[29] b7 i/o d10 i/o j1 i/o p4 i/o v3 i/o y6 ad[25] b8 i/o d11 vcc j2 i/o p17 i/o v4 ad[30] y7 ad[23] b9 i/o d12 i/o j3 nc p18 i/o v5 ad[28] y8 ad[19] b10 i/o d13 gnd j4 i/o p19 nc v6 ad[24] y9 ad[17] b11 i/o d14 i/o j17 nc p20 i/o v7 idsel y10 irdyn b12 i/o d15 vcc j18 i/o r1 nc v8 ad[18] y11 i/o b13 i/o d16 i/o j19 i/o r2 i/o v9 ad[16] y12 serrn b14 i/o d17 gnd j20 gclk/i r3 i/o v10 trdyn y13 ad[14] b15 i/o d18 i/o k1 i/o r4 vcc v11 stopn y14 ad[12] b16 i/o d19 i/o k2 i/o r17 vcc v12 vccio y15 ad[8] b17 nc d20 i/o k3 i/o r18 i/o v13 ad[15] y16 ad[7] b18 stm e1 nc k4 vcc r19 i/o v14 ad[13] y17 ad[3] b19 nc e2 i/o k17 gclk/i r20 i/o v15 cben[0] y18 i/o b20 i/o e3 i/o k18 aclk/i t1 nc v16 ad[6] y19 i/o c1 i/o e4 i/o k19 gclk/i t2 i/o v17 ad[2] y20 nc c2 i/o e17 i/o k20 nc t3 i/o v18 i/o c3 i/o e18 i/o l1 clk t4 nc v19 tms
? 2005 quicklogic corporation www.quicklogic.com ql5130 quickpci data sheet rev. e 25 ordering information contact information phone: (408) 990-4000 (us) (905) 940-4149 (canada) +(44) 1932 57 9011 (europe ? except german y/benelux) +(49) 89 930 86 170 (germany/benelux) +(86) 21 6867 0273 (asia ? except japan) +(81) 45 470 5525 (japan) e-mail: info@quicklogic.com sales: www.quicklogic.com/sales support: www.quicklogic.com/support internet: www.quicklogic.com revision history revision date originator and comments rev. a september 1999 rev. b december 1999 rev. c july 2004 bernhard andretzky and kathleen murchek converted to new format. added summary to pinout tables. rev. d july 2005 jason lew, mehul kochar and kathleen murchek changed pin 27 from clk to vcc on ql5130 - 208 pqfp pinout table. added ordering information section, including lead-free packaging option. rev. e september 2005 mehul kochar and kathleen murchek updated ordering information section to include parts 208 pqfp and 256 pbga as having lead free packaging. ql 5030 -a pf144 c operating range: c = commercial i = industrial package code: pf144 (pfn144)* = 144-pintqfp pq208 (pqn208)* = 208-pin pqfp pb256 (pbn256)* = 256-ball pbga part number quicklogic device speed grade * lead-free packaging is available, contact quicklogic regarding availability (see contact information).
www.quicklogic.com ? 2005 quicklogic corporation ql5130 quickpci data sheet rev. e 26 copyright and trademark information copyright ? 2005 quicklogic corporation. all rights reserved. the information contained in this docu ment is protected by copyright. all rights are reserved by quicklogic corporation. quicklogic corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. copying, dupl icating, selling, or otherwise distributing any part of this product without the prior written consent of an au thorized representative of quicklogic is prohibited. quicklogic and the quicklogic logo, pasic, quickram , vialink and quickworks are registered trademarks the quicklogic corporation; spde and quicktools are trademarks of the quicklogic corporation. verilog is a registered trademark of cadence design systems, inc.

▲Up To Search▲

Price & Availability of QL5130-33APQ208C

	To Download QL5130-33APQ208C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .